Overview
Reduced Energy Microsystems (REM) was a San Francisco-based fabless semiconductor startup founded in 2014 by William Koven, Eleazar Vega-Gonzalez, and Dylan Hand. [1] The company built ultra-low-power chips for embedded machine learning inference at the edge — targeting applications like police body cameras, security systems, drones, and augmented reality devices — using asynchronous circuit design, a decades-old academic approach that eliminates the master clock governing conventional chips. [2] REM entered Y Combinator's Summer 2015 batch as the accelerator's first chip startup. [3]
REM failed because asynchronous chip development — despite genuine technical merit — requires capital-intensive, multi-year development cycles that a $2M seed-funded startup could not sustain long enough to reach commercial scale. The edge AI inference market it was targeting simultaneously attracted well-funded incumbents and specialists who commoditized the space before REM could ship at volume.
Crunchbase lists REM as permanently closed as of August 21, 2020 — roughly six years after founding and approximately three years after its last documented public activity. [4] No acquisition, acqui-hire, or public post-mortem was announced. Koven subsequently joined Galois, Inc. as a research engineer before becoming a chip lead at Meta; Vega-Gonzalez went on to found Coil, a builder AI startup that entered YC's Winter 2023 batch. [5] [6]
Image 1 / 3
Founding Story
Reduced Energy Microsystems emerged from a specific convergence of academic research, industry frustration, and a window in the semiconductor market that the founders believed incumbents were structurally unable to exploit.
William Koven, the CEO, came to the founding with direct industry experience. He held a B.S. in Engineering from Harvey Mudd College, where he was a Clay-Wolkin Fellow, and had spent years at Intel before co-founding REM. [7] [8] His time at Intel gave him a close-up view of why large semiconductor companies resist architectural change: the organizational and toolchain investments in synchronous design are so deep that alternatives — even technically superior ones — get rejected on institutional grounds. "Asynchronous is kind of a dirty word at Intel," Koven later said. "It's just too different from what they do as an organization. They've thrown out a lot of technologies like this because they're different and scary." [9]
Dylan Hand was a Ph.D. student at USC's Viterbi School of Engineering, where he worked in the E2S2C (Energy-Efficient Systems, Circuits, and Chips) lab — the academic home of asynchronous VLSI research at USC. [10] The lab had a prior commercialization lineage: TimeLess Design Automation, an asynchronous EDA startup spun out of the same research group, had been acquired by Fulcrum Microsystems, which was itself acquired by Intel in 2011. [11] That chain of acquisitions suggested that asynchronous chip IP had real value — but also that the path to standalone company success in this space was historically difficult.
Eleazar Vega-Gonzalez studied Electrical and Computer Engineering and Computer Science at Carnegie Mellon University and took on the Head of Software and Commercialization role at REM. [12] His background bridged the hardware-software divide that REM was explicitly trying to close — the company's go-to-market strategy depended on making asynchronous chips accessible to software developers who had never thought about clock domains.
The founding insight was straightforward: the explosion of always-on, battery-powered devices running computer vision and machine learning workloads created a power efficiency problem that conventional synchronous chips were poorly suited to solve. Asynchronous circuits, which only consume power when performing actual computation rather than on every clock tick, offered a structural solution. The team's specific contribution was making that solution compatible with existing industry toolchains — "when we implement an ARM core, it still looks like an ARM core to the programmer," Koven explained. [13]
REM joined YC's Summer 2015 batch, becoming the accelerator's first chip startup. [14] The team later added Peter Beerel — the USC Viterbi professor who led the E2S2C lab — as Chief Scientist, and Georgios Dimou, a co-founder of TimeLess Design Automation and former Intel Labs engineer, as Chief Architect. [15] [16] Dimou had lived through the prior asynchronous chip startup cycle firsthand — a fact that gave REM institutional memory about the failure modes it was trying to avoid, even if that memory ultimately proved insufficient.
Timeline
- 2014 — Reduced Energy Microsystems founded by William Koven, Eleazar Vega-Gonzalez, and Dylan Hand. [1]
- June 2015 — REM enters Y Combinator Summer 2015 batch, becoming YC's first chip startup. [2]
- September 2015 — YC Demo Day period; Draper Associates funds a $2M seed round via YC introduction. [17]
- 2016 — Peter Beerel (USC Viterbi asynchronous VLSI professor) joins as Chief Scientist; Georgios Dimou (ex-TimeLess, ex-Intel Labs) joins as Chief Architect. [15] [16]
- March 16, 2017 — TechCrunch publishes the company's most prominent press profile; chip creation described as largely complete, with product integration testing underway and prototypes expected by end of 2017. [8]
- June 9, 2017 — REM receives a $224,576 NSF grant. [18]
- November 28, 2017 — REM joins the RISC-V Foundation, signaling a strategic move toward the open-ISA ecosystem. [19]
- December 5, 2017 — REM joins GLOBALFOUNDRIES' FDXcelerator Partner Program and announces RISC-V CPU IP availability on GF's 22FDX process — the company's last documented public activity. [20]
- August 21, 2020 — Crunchbase lists REM as permanently closed. No public announcement or post-mortem issued. [4]
What They Built
REM's core product was a family of ultra-low-power chips designed to run machine learning inference workloads — primarily computer vision tasks like facial recognition and object detection — directly on battery-powered edge devices, without sending data to the cloud.
The technical foundation was asynchronous circuit design. In a conventional synchronous chip, every transistor in the circuit switches on every clock tick, regardless of whether it has useful work to do. This wastes power proportional to the clock frequency. An asynchronous circuit, by contrast, has no master clock: each logic block signals its neighbors when it has completed a computation, and the next block begins only when triggered. The result is that power is consumed only when actual computation occurs — a meaningful efficiency gain for workloads like always-on video monitoring, where the chip spends most of its time waiting for something interesting to happen. REM claimed 3–4x or greater energy efficiency improvements over conventional chips of equivalent capability, depending on the application. [21]
The practical challenge with asynchronous design has historically been toolchain incompatibility. Standard electronic design automation (EDA) tools — the software used to design, simulate, and verify chips — are built around synchronous assumptions. REM's key engineering contribution was developing an internal tooling layer that allowed asynchronous circuits to be designed and verified using the same industry-standard EDA tools that synchronous chip designers already used. [22] When REM implemented a standard processor core like an ARM design on their process, the resulting chip still presented a familiar interface to the software developer writing code for it. This was the company's primary answer to the integration friction that had historically prevented asynchronous chips from reaching production.
REM's target applications were edge devices with constrained power budgets running continuous sensing workloads: police body cameras, security cameras, DVRs, drones, augmented reality headsets, and autonomous robots. [23] [24] These were markets where battery life was a genuine constraint and where on-device inference — rather than cloud offload — was either required (latency-sensitive applications) or strongly preferred (privacy-sensitive applications like body cameras).
By March 2017, the company had completed chip design and was in product integration testing, with customer prototypes expected by the end of that year. [25] At least one chip had been built for a specific customer, though the customer's identity and whether this led to commercial revenue was never disclosed. [26]
In late 2017, REM made a notable strategic shift. In November, it joined the RISC-V Foundation. [19] In December, it announced a partnership with GLOBALFOUNDRIES' FDXcelerator program to offer low-power RISC-V CPU IP on GF's 22FDX process node — a 22-nanometer fully-depleted silicon-on-insulator technology optimized for low-power IoT applications. [20] This pivot from selling custom ASICs to licensing processor IP represented a meaningful change in business model: rather than building and selling complete chips, REM would offer its asynchronous RISC-V core as a building block that other chip designers could integrate into their own system-on-chip designs. Whether this pivot generated any design wins or revenue before the company closed is unknown.
Market Position
Target Customers
REM's primary customers were manufacturers of battery-powered edge devices that needed to run computer vision or machine learning workloads locally. The company specifically named police body camera manufacturers, drone makers, DVR and security camera vendors, and AR device developers as its target markets. [23] [24]
These customers shared a common profile: they were building devices where battery life was a first-order constraint, where the compute workload was dominated by continuous video analysis, and where the cost of cloud connectivity — in latency, bandwidth, or privacy exposure — was prohibitive. A police body camera that could run facial recognition locally without draining its battery in two hours, or a security camera that could detect intruders without sending a continuous video stream to a cloud server, represented genuine product improvements that customers would pay for.
The secondary customer profile, emerging from the late-2017 RISC-V pivot, was semiconductor companies designing IoT SoCs who needed a low-power processor IP core they could license and integrate. This is a smaller, more technically sophisticated customer base with longer sales cycles but potentially higher contract values.
Market Size
The edge AI inference chip market was nascent but growing rapidly during REM's operating years. The broader IoT chip market was projected to reach tens of billions of dollars annually by the early 2020s, with the AI-at-the-edge segment representing an increasingly significant share as machine learning models were compressed and optimized for deployment on constrained hardware. The specific verticals REM targeted — security cameras, body cameras, drones — were each multi-billion-dollar hardware markets with meaningful chip content per device.
The IP licensing market for processor cores, which REM was moving toward in 2017, is dominated by ARM Holdings, which licenses its architecture to hundreds of chip designers globally. RISC-V represented an open-source alternative that was gaining momentum in IoT and embedded applications, and the market for RISC-V IP was beginning to develop commercial structure around 2017–2018.
Competition
REM's competitive position is best understood along two axes: power efficiency (where asynchronous design offered a genuine structural advantage) and time-to-market and distribution reach (where incumbents and better-funded startups held decisive advantages).
On the power efficiency axis, REM had a real differentiator. Incumbent chip makers — Intel, Qualcomm, ARM licensees — had long known about asynchronous design but were institutionally locked into synchronous architectures. As Koven observed, the organizational investment in synchronous toolchains, verification flows, and design teams made it effectively impossible for large companies to pivot, regardless of the technical merits. [27] This was a genuine innovator's dilemma dynamic — but it was also a double-edged observation. If incumbents couldn't compete on asynchronous design, they could still compete on synchronous design improvements, process node advances, and the distribution advantages that come with existing customer relationships.
On the time-to-market axis, REM faced a structural problem. The edge AI inference market was simultaneously being targeted by companies with far greater capital: Movidius (acquired by Intel in 2016 for a reported $400M) had already shipped its Myriad 2 vision processing unit to customers including DJI and Google. Qualcomm's Snapdragon 820 included a dedicated neural processing unit. Later entrants like Hailo, Syntiant, and Eta Compute — all better funded than REM — were pursuing similar low-power inference positioning. These competitors could absorb multi-year development cycles because they had the capital to do so; REM could not.
The RISC-V/IP licensing pivot in late 2017 can be read as an implicit acknowledgment that competing directly on chip sales against these players was not viable. IP licensing offered a faster path to revenue and a different competitive frame — but it also meant competing against established RISC-V IP vendors like SiFive (founded 2015, raised $64M by 2018) on a dimension where REM's asynchronous advantage was less clearly differentiated.
The structural reality was that REM was competing in a market where the winning strategy required either (a) enough capital to survive a 5–7 year development and customer acquisition cycle, or (b) a faster path to revenue through IP licensing or acquisition. REM had neither the capital for the former nor, apparently, the traction for the latter.
Business Model
REM's intended revenue model was fabless chip sales: design chips, have them manufactured by a contract foundry (a "fab"), and sell them to device manufacturers. This is the standard fabless semiconductor model used by companies like Qualcomm, NVIDIA, and AMD. Revenue per chip varies widely by application and volume, but for specialized AI inference chips targeting industrial and commercial markets, average selling prices in the $5–$50 range per unit are typical at moderate volumes.
The late-2017 pivot toward RISC-V IP licensing represented a shift to a royalty-based model: charge chip designers a one-time license fee plus a per-unit royalty for the right to integrate REM's processor IP into their own chips. This model has lower capital requirements (no tape-out costs for the licensor) but requires building a sales and support infrastructure for a technically sophisticated customer base.
REM never disclosed revenue figures. The absence of any revenue disclosure across six years of operation is itself a signal — companies that achieve meaningful commercial traction typically reference it in press coverage, even without disclosing exact numbers. No such reference appears in any documented source.
On capital efficiency: Crunchbase lists total funding of approximately $2.12M (the $2M Draper seed plus the $224,576 NSF grant), though PitchBook lists a conflicting figure of $120K, suggesting incomplete public records. [18] [28] Taking the Crunchbase figure as the more complete estimate, and assuming a team of 7 people (as documented) at average fully-loaded costs of approximately $150K–$200K per person annually, REM's annual burn rate would have been roughly $1–1.5M — implying that the $2M seed round provided approximately 16–24 months of runway. This is an inference based on headcount and industry compensation norms, not disclosed financial data. A single ASIC tape-out on an advanced process node can cost $500K–$5M, which would have consumed a substantial fraction of total capital in a single event.
No Series A or follow-on institutional round is documented anywhere. This is the most significant financial signal in REM's history.
Post-Mortem
Primary Cause: Structural Capital Insufficiency for Semiconductor Development
The most important fact about REM's failure is the simplest: the company raised approximately $2M to build custom silicon, and $2M is not enough money to build custom silicon at commercial scale.
A single ASIC tape-out on a modern process node costs between $500K and $5M depending on the node and design complexity. EDA tool licenses for a small team run $200K–$500K annually. Foundry engineering support, packaging, testing, and qualification add further costs. Before REM could sell a single chip to a paying customer, it had to spend most of its capital on development infrastructure. The NSF grant of $224,576 in June 2017 — roughly two and a half years after founding — provided a meaningful but not transformative supplement. [18]
The absence of a Series A is the clearest evidence that this capital problem was not solved. Semiconductor startups that achieve technical milestones and early customer traction typically raise $10–$30M Series A rounds to fund the transition from prototype to production. REM's last documented public activity was in December 2017; it closed in August 2020. The approximately 32-month gap between last press activity and closure, with no funding announcement in between, is consistent with a company that was unable to raise additional capital and was slowly exhausting its remaining resources. No investor or founder statement confirms this interpretation, but no alternative explanation is documented.
Koven's framing of the Draper investment is instructive: "For Draper… they really believe in the future we're trying to enable. They see it's going to take more than software to do that. And the semiconductor industry is stagnating in so many ways." [17] This is a mission-alignment pitch, not a unit economics pitch — suggesting that the seed round was funded on vision rather than demonstrated commercial traction, and that subsequent investors applying more rigorous commercial criteria may have passed.
Secondary Cause: The Asynchronous Chip Startup Failure Mode Is Well-Documented
REM's founders were aware of the historical failure pattern for asynchronous chip startups. Vega-Gonzalez acknowledged it directly in March 2017: "It's been tried a few times and historically what's happened is you see these benefits but it takes way longer to get to market." [29]
The USC Viterbi lineage makes this concrete. TimeLess Design Automation, the prior asynchronous EDA startup from the same research group, was acquired by Fulcrum Microsystems, which was then acquired by Intel in 2011. [11] The outcome for TimeLess was not failure in the conventional sense — the IP was valuable enough to be acquired twice — but it was also not standalone company success. The IP ended up absorbed by an incumbent, which is precisely the outcome that REM was trying to avoid by building a complete chip product rather than just EDA tools.
REM's Chief Architect, Georgios Dimou, had lived through the TimeLess cycle. [16] His presence on the team suggests the founders understood the failure mode and believed they had addressed it — through toolchain compatibility, through targeting a specific application market rather than selling general-purpose EDA tools, and through the RISC-V pivot. The fact that the company still closed without a public success suggests these mitigations were insufficient.
Tertiary Cause: The Edge AI Market Moved Faster Than REM Could
REM's target market — low-power edge inference chips — was real and growing. But it was also attracting capital at a scale that REM could not match.
Movidius, which built the Myriad 2 vision processing unit, was acquired by Intel in 2016 for a reported $400M. By the time REM was still in prototype testing in late 2017, Myriad chips were already shipping in DJI drones and Google's Project Tango devices. Qualcomm's Snapdragon 820, released in 2016, included dedicated neural processing capability. The market was not waiting for REM.
The companies that succeeded in edge AI inference chips — Hailo (raised $136M by 2021), Syntiant (raised $35M by 2020), Eta Compute (acquired by Nordic Semiconductor in 2021) — all raised substantially more capital than REM and had longer runways to navigate the same development cycle. REM's asynchronous approach may have offered a genuine efficiency advantage, but efficiency advantages in chips are only commercially relevant if you can get to market. REM's competitors got there first, with more money.
Structural Factor: The Software-Startup Playbook Does Not Apply to Semiconductor Companies
YC's institutional approach — move fast, talk to customers, iterate quickly — is well-suited to software companies where the marginal cost of a new version is near zero. It is poorly suited to semiconductor companies where each design iteration requires a tape-out that costs hundreds of thousands of dollars and takes months to return from the foundry.
Vega-Gonzalez described the tension directly: "There was kind of a consistent push to move quickly and focus on the business and customer relations kind of thing." [30] REM's response was to invest heavily in internal tooling to compress development cycles: "Something we've emphasized a lot is our internal tooling, so that we can move faster than the rest of the industry — which is exactly what lets software startups beat or exceed bigger companies." [31]
This was a genuine strategic insight. But semiconductor development cycles have structural floors that tooling improvements can compress but not eliminate. Physics, not process, governs how long it takes to design, tape out, fabricate, package, test, and qualify a chip. A software startup can ship a new version in a week; a chip startup cannot tape out a new design in a week regardless of how good its internal tools are. The YC model's emphasis on speed created pressure that was ultimately incompatible with the development timeline of the product REM was building.
The Late Pivot: Necessary but Possibly Too Late
The RISC-V Foundation membership and GLOBALFOUNDRIES partnership announced in late 2017 suggest REM recognized that direct chip sales were not generating sufficient revenue and that IP licensing offered a faster path. [19] [20] This was a reasonable strategic adjustment — IP licensing requires less capital per revenue dollar than chip manufacturing and can generate recurring royalty income.
But the pivot came approximately two years after the seed round, by which point REM's runway was likely severely constrained. Building an IP licensing business requires a different sales motion, different customer relationships, and different technical support infrastructure than selling chips. Executing that transition with limited capital and no documented follow-on funding was a significant challenge. The absence of any press coverage, partnership announcements, or design-win disclosures after December 2017 suggests the pivot did not generate the commercial momentum needed to attract additional investment.
Key Lessons
-
Asynchronous chip IP has historically been absorbed by incumbents rather than generating standalone company success, and REM's lineage made this outcome predictable. TimeLess Design Automation — the prior asynchronous chip startup from the same USC Viterbi research group — was acquired by Fulcrum Microsystems, which was then acquired by Intel. REM's Chief Architect had lived through that cycle. The pattern suggests that asynchronous chip technology is valuable enough to be acquired but not differentiated enough in go-to-market execution to sustain an independent company against incumbents with distribution advantages. A licensing-first strategy from day one — rather than a pivot to it in year three — might have produced a different outcome.
-
REM's $2M seed round was structurally insufficient for a fabless semiconductor company, and the failure to raise a Series A was the proximate cause of closure. Semiconductor companies that successfully commercialize novel chip architectures — Hailo, Syntiant, Eta Compute — raised $35M–$136M before reaching production scale. REM's total documented capital of approximately $2.1–2.3M could not fund the tape-out costs, EDA tool licenses, and multi-year development cycles required to reach the same milestone. The lesson is not that chip startups shouldn't raise from YC, but that the capital requirements of semiconductor development are categorically different from software, and seed-stage funding alone is rarely sufficient.
-
The YC "move fast" framework created productive pressure on REM's tooling strategy but could not compress the physics of chip development. Vega-Gonzalez explicitly described YC's push to move quickly and focus on customer relations — and REM's response was to invest in internal tooling to accelerate iteration. This was the right instinct, and it may have genuinely compressed REM's development timeline. But the structural floor on chip development cycles — tape-out lead times, foundry queues, packaging and testing — cannot be tooled away. Startups applying software-startup frameworks to hardware problems should model the irreducible timeline floors explicitly before committing to a capital structure.
-
REM's RISC-V pivot in late 2017 was strategically sound but arrived too late in the company's capital cycle to be executed effectively. IP licensing requires less capital per revenue dollar than chip manufacturing, and the RISC-V ecosystem was growing rapidly in 2017–2018. But REM announced the pivot approximately two years after its seed round, with no documented follow-on capital and no subsequent press coverage suggesting design wins. The lesson is that business model pivots in capital-intensive hardware companies need to be executed while sufficient runway remains to build the new sales motion — not as a last resort when capital is nearly exhausted.
-
The edge AI inference chip market rewarded companies with the capital to survive long development cycles, not necessarily those with the best technology. REM's asynchronous approach offered a genuine 3–4x power efficiency advantage over synchronous alternatives. [21] But Movidius shipped Myriad chips to DJI and Google before REM had prototypes, despite using conventional synchronous design. In semiconductor markets, time-to-market and distribution relationships often matter more than architectural elegance. Technical differentiation is necessary but not sufficient; capital to survive the development cycle is the binding constraint.
Sources
- Crunchbase — Reduced Energy Microsystems
- Y Combinator — Reduced Energy Microsystems
- TechCrunch — "Reduced Energy Microsystems Pits Startup Chip Chops Against Industry Giants" (March 16, 2017)
- Crunchbase — Reduced Energy Microsystems Financial Details
- NanoHub — William Koven profile
- IEEE CEDA — Peter Beerel contact page (references Dylan Hand and REM)
- Topio Networks — Eleazar Vega-Gonzalez profile
- Topio Networks — Georgios Dimou profile
- CBInsights — Reduced Energy Microsystems
- USC Viterbi E2S2C Lab — Asynchronous VLSI research
- PRWeb — REM joins RISC-V Foundation (November 28, 2017)
- PRWeb — REM joins GLOBALFOUNDRIES FDXcelerator Program (December 5, 2017)
- InKnowVation / SBIR — Reduced Energy Microsystems team listing